Quote...move forward with our next board design!And we are on rev 3 of the board.
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Show posts MenuQuote...move forward with our next board design!And we are on rev 3 of the board.
QuoteDoes this still exist? Link is down.It's still up on the aetherbyte site. Just check and link worke fine for me.
QuoteI'm certain that the "additional" memory goes to $7F, to make memory contiguous.Okay. Being wrong is part of learning.
QuoteThat I already have and use it from time to time, if you want it.Yes, please.
QuoteOr make bi-compatible hucards. Function as normal hucards, or enhanced if used on a CD systemOr add extra levels on the cd...
QuoteOK guys, you're scaring me here ... and I missing something crucial, or are we talking about different things?I don't think we're talking different things.....
QuoteWell, 8 levels deep with 4 ints per level is 64 bytes. Well within a 128 byte stack.I guess I just don't get the point of using a zp stack area.
QuoteIf you're doing that in HuC, then you're generating some pretty slow and ugly code ... unless everything is already declared as a static.Slow ugly code wasn't a problem while we were developing it, but yes, things got moved to static (ie ram) variables as part of the optimization process
QuoteI take it that you really mean "[temp],y" to access them. I guess that I'm missing something again. How is that an improvement over the current HuC "[stack],y"?no, i really meant temp,x....but maybe I didn't exactly explain it clearly. The thought was to do it the same way most tia/tai/tii etc instructions are done; set up a small routine, with the address as a variable. Then you could call the routine to get the value. I realize its probably not faster, but it's doable. Hey, not all my ideas are -good- ones
QuoteImproving either HuC or CC65's actual internal optimization would be great, but is beyond my interest level.No, not the internal optimization. A seperate optimizer program. That goes through the code (from either HuC or CC65 and rearranges/rewrites it in a more optimized form. Which you then assemble and/or link.
QuoteOddly enough, I think its actually the way Huc parses declarations and generates code.QuoteDo you know why huc include a dummy .dw between each datas included ??I'm not 100% sure whether I'm clear on what you're asking, but it could be to force 16-bit alignment on 16-bit word data. At least, I seem to recall there was something like that.
QuoteWell, it's not as cramped as that, but the system card does allocate from the bottom up, and the top down.Okay. I just checked and there's an area between $90 and $DC that's not being used, afaik.
QuoteSo, I would anticipate people passing 4 int variables in a function call. I would anticipate 8-deep call levels. And so I would anticipate corruption of variables due to exhausting all memory. The target code would fail without warning (because who's going to put bounds checks in there ?), and the user would blame the compiler for his problems+1. 8 deep level calls is not that unusual; 4 ints as parameters isn't either (consider Rovers 'example', where there are several variables, for setting up a sprite).
QuoteNot unless we're reading different manuals.I'm not reading a manual. I'm looking at the system card code.
QuoteWith a zero-page based stack you can take full advantage of the 65C02's instruction set and use "zp,x" (just look at the timings and the extra instructions).or, given X is an offset, you could generate labels for the entire stack area, and access values as
QuoteOK, next question ... what do people use zero-page for, and how full does it get?Mostly, addresses for indirect access, and high useage variables.
QuoteWhat do you think about putting C stack in zero-page (there are lots of advantages to the code)?Why?
QuoteYeah, I set _DH to the MPR page and put the starting bank in _BL.lda #4 ; $8000 range / sta _DH / lda #80 /sta BL kinda thing?
QuoteOk. I tracked down the problem with BRAM code.Good to hear. Now, when can we expect Dragon Warrior?
QuoteIt's definitely an emulator thing with mednafen. I switched over to using the sys card bram routines instead,...That sounds so damn familiar...I wish I could remember what we did to fix it...
QuoteAlso, the CDREAD routine is annoying. I can only read in as many free banks as I have logical address range for (32k at a time)The syscard 3.0 (?) CD_READ uses DH as a read type; the nice (or not) thing is you can specify an MPR bank to use for the read, and it is capable of filling consecutive banks for you.
QuoteOk, so I just tried it with bank $69 in mpr7 and bank $f7 in mpr4.Okay. One more silly observation, then I'll leave it alone.
QuoteMPR2 is the $4000 cpu range, iirc.My bad. I was just looking at something else, and noticed the syscard bram functions
QuoteAnd in the CD project the bram code is in bank $69 and MPR 2. I'll MPR7 and see if that has any effect.Hunh? MPR2 is the $4000 cpu range, iirc. I'd have to trace through that stuff again, but I think thats actually where the BRAM 'appears' (I could be wrong, though)
QuoteSeems I'm running into a problem using the same BRAM libs from a CD project.It seems to me that if it works for a Hucard project, it should work for a CD project.
QuoteIMHO, it's not worth my time and energy to mess with one of the compilers...Just out of curiosity, have you thought about adding a seperate optimizer to the tool chain?
QuoteFrom what I'm seeing, all the math macros like compare, add, subtract, shift, multiply, etc are all hard-coded for 16-bit values in X:A.Probably. I think it would be hard enough to get right in a limited case, much less write a macro that handles all the possibilities. (But then, I'm not that good at asm. I have enough trouble with compares when I know the sizes <lol>)
QuoteThat is what the last patch I made to HuC does, since I was working on the 240p test suite version for system card 1.0.Someone should really gather all the patches together, and release an updated HuC.
QuoteShould I be looking in the code-generator itself?Its not how HuC generates the code; it basically generates macro calls to do things, iirc.
Quoteit looks like everything is done as 16-bit values.Not quite. Some (most?) of the macros check the size of the given value, and omit the high byte code if a char gets passed.
QuoteIf you do some work with HuC, adding these feature would really help it out IMO.I'd settle for it remembering how much space is empty in each bank, and trying to fit functions in where
QuoteIt looks like there's a bank for constants ... not sure why. What else? Where do they go?There's a bank for constants; I assume its because they can be mapped in and out when needed. I believe thats bank 3, but i could be wrong.
QuoteI could never understand why Tandy released the CoCo3 ... but then I wasn't in America at the time.I think a lot of that was trying to give the diehards what they wanted.
QuoteNaturally, CoCo3 users found out about this CPU's secret and put them into their Cocos.Yeah. The 6309 mod is probably the only one I was afraid of trying <sigh>. At that age (20's), removing a CPU was frightening. Though I might have tried it if someone had made a dual CPU switchable board...
QuoteIt was the computer I had when I was a kid (CoCo 2 and CoCo 3). Though I couldn't afford OS-9.Still got it?
QuoteI think that you may be thinking of a few years later,Ok, my bad. Just asked the nephew to verify, and he says he was in middle school (7-9 grade). Sine he was born in 81, that would make it 93-94.
QuoteThis was written in 1991. CD-R technology was very new, and burners cost approx $30,000.Uh, no. My first burner (a 1x ricoh) was about $500. Throw in the scsi card needed to run it at another $200. Heck, Throw in the pc, too, at $2500.
QuoteHmm. Maybe I could even go a step further with __GetBRAMByte, and have the return jump be from a table. And the index (into the jump table) would be the register in which the function that called it, would set the return address.I did something sort of like that once; fix stack pointer, then get the return address from a table and push it. Then when the function returned, it went back to the chosen function.
Quoteas far as trace routing, that was mostly done by handYou have more patience than I do.
QuoteSo you're saying that they stole the internal pcb design?You do know that circuit design software will lay out the traces for you, don't you?
Quote.... would smell worse than bigfoots dick.How would you know that?
QuoteOn that note: does the system card take care of defragmenting the entries?I take my comment back. I just checked, and it looks like it shifts the directory/data blocks backwards, over writing the old data, and adjusts the available pointer.
QuoteSo what about the linked list system? Is there a WORD pointer at the end of an entry?Don't believe so. It adds up the entry sizes. Recognizes list end by comparing to next available byte.
QuoteOn that note: does the system card take care of defragmenting the entries?<lol>. No, I don't think it does.
QuoteMine sometimes has an issue erasing the romIf thats about the gameofyou cheap flash card.... try lightly resting a finger on the left chip, and see if that helps.
Quoteas far as 5V it wouldnt be required on the cpld as the RAM can be 5V and drive the outputs+1 problem solved.
a 3.3v chip can address a 5V chip fine
QuoteIMHO, you should only need a fairly simple FPGA/CPLD to do the Arcade Card ... your problem is more going to be in the number of I/O pins that you need, and the total number of individual IC chips ... trying to fit a CPLD, ROM, and 2 RAM chips into the space that you've got is going to be ... interesting.I agreee. But there's room for 2 memory chips (Ram or Rom) underneath the board; then you have the
QuoteSs far as CPLD/FPGA/RAM choices, well you don't have that many anymore if you're talking about using 5V parts...Always a problem with older systems, unfortunately.
QuoteIs the Arcade Card Pro really that rare that it's worth going to all that trouble?Probably not. It's a Nice design problem, though.
QuoteErrr ... don't we already have that "super" Arcade Card with the Turbo Everdrive 2?Not that I am aware of. Doesn't the arcade card have extra registers? (I'm pretty sure there is at least a shift register available.) Are those emulated on the TED 2?
Quote...as far as space we have about 0.040 chip height to play with and are using TSOP nowHeight isn't the problem; we know theres enough room underneath for Flash / Ram chips. (Rams are same height at Flash; Flash chip fit underneath, so there's no problem).
Quote... new, cheap, repro Arcade cardYes it can probably be done. Would need a programmable chip (PGA/CPLD) to do the registers, and
Quote..4bits=nibbleActually, half a byte is a nibble
QuoteI wonder if I could get credit for "independent study" course if I worked on HuC. Heh.Probably. That's how Insanity started....
Quotepins4 and 30-32 concern meThat's A16, A13, A14, and A17, right? During boot up it reads page 0, so I could see those being 0V.
Quotei thought that was without cardWouldn't you see 0's without the card?
QuoteEasily explained. He had hundreds of copies he couldn't get rid of, but 50 that he could get rid of. Those are the ones that were sold; he still has the hundreds that he cannot get rid if.Sorry, I read that differently. I read "He has (had) hundreds of copies; the 50 he had listed sold out in 24 hrs.". Possibly he still has another 50 or so to go