12/06/2023: Localization News - Tengai Makyou/Far East of Eden: Ziria!!!

OMG! ZIRIA! ZIRIA!!! IT ACTUALLY HAPPENED!! 34 YEARS LATER!! The epic/legendary Tengai Makyou/Far East of Eden: Ziria JRPG has finally been localized! Supper the Subtitler struck again! Simply unstoppable, NOTHING can prevent him from TOTAL PCECD localization domination!!!! WHACHA GONNA DO BROTHER?!?!
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Messages - Pierre95

#1
Thanks a lot elmer, both links are really helpfull.
#2
Hello,

Line A20 of HuC6280 is named XCE on the Hucard connector. This line is used as the ROM chip select. This is OK for 1MB or smaller ROMS as all ROMs fit this size, except street fighter II which is 2,5MB. This means this ROM requires some memory banking to allow reaching the extra segments which dos not fall in the 21 bits addressable space, right?

I am a bit confused about the addressable segments.

Here http://emu-docs.org/PC%20Engine/pce_doc/pce_memory.html

It is written Hucard storage goes till F6h =1968KB

But here http://www.db-elec.com/home/technical-info/tg16/memory-map

it says the space between 80h and F7h is unused (reserved for CD ROM) so what is the truth about that?

Also here: http://emu-docs.org/PC%20Engine/hw.html

It seems segments 01 of ROM is unused, but when looking into a ROM file through hexeditor, there is data in this segment...
#3
@elmer

The documentation at http://archaicpixels.com/HuC6280 does not specify the state of the address bus when /RESET is low but the documentation says:

Quote/RESET terminal
A program is started by reading lower address from the physical address 0x001FFE and upper address from the physical address 0x001FFF when a RESET input becomes Low.
Which can be interpreted as "the processor outputs the physical addresses 0x1FFE and 0x1FFF when /RESET is low" So the address bus is probably not at high impedance when /RESET is low. But as you say elmer, it should be verified through experimentation.

@NightWolve, yes the Everdrive is a great product but for educational purposes, I find it interesting to design a similar hardware.
#4
OK thank you for that precision.

If only we could get the 6280 CPU specification from NEC/Hudson... Don't know if the 6502 specifications can be considered as the 6280 Address bus can have different behaviour due too specific implementation.

The design would also have to manage isolation for control signals (/OE, /R)
#5
OK so the SELECT+RUN command initiates a software reset, but only an hardware reset puts for sure both the address and data buses in a high impedance state for the whole time the XRESET pin is low.
#6
Thanks a lot for your support

Driving the XRESET signal while programming is probably a good solution provided it puts unconditionally the address and data bus of the CPU in high impedance state.

The XRESET pin is mentionned as an input, but what happens when initiating a reset with the SELECT+RUN keys? Does XRESET remain an input, or a short pulse initiated by the CPU appears to reset other ICs like the 6270?

PSoC 5 has too much options for the expected usage, in my point of view...
#7
You mean the PC engine CPU flashing it's own Flash EPROM? Well but this requires some bootloader residing in an unerasable segment of the Flash.

However even the FTDI USB to FIFO solution requires some isolation logic to avoid conflicts beteen the FTDI output and the databus of the CPU. And the Turbo Everdrive has a generous FPGA with plenty of logic for glue purposes.
#8
Hello,

Thank you for your replies. I aldready had some discussions with the guy from gamingenterprisesinc. His design is simple and use very few components however it requires removing the card from the console while Flashing to avoid conflicts between the console buses and the PIC IO ports. A similar conflict exists between VCC from console and USB VCC.

I was guessing if the CARD DETECT signal was not used internally to maintain the CPU in a halted/high impedance state till the insertion of an HuCard. This could be used to solve the conflict mentionned above.

But from your answer, I understand that the signal is only used to toggle between a built-in system card 3 accessed through expansion bus, and the Hucard (Hucard has priority over Card 3 ROM). This means the CPU is constantly driving the address bus even when no HuCard is inserted.
#9
Hello,

I recently put a PC engine GT back to life by changing its capacitors and found it would be interesting to design a Flash based Hucard so that games could be downloaded through USB.

However, I have questions about the signal named XCHECK corresponding to HuCard pin number 1.

According to turbografx schematics, this pin is pulled up through a 4,7K resistor, but I didn't find the component (IC) where this signal is connected. XCHECK should inform the system that a card is inserted.

What is the state of address and databus when no card is connected? Is it high impedance?

Thanks a lot if someone can provide some help.